Allied Minds

  • Spin Memory - Senior Design Verification Engineer

    Job Locations US-CA-Fremont
    Posted Date 4 weeks ago(11/12/2018 11:40 AM)
    Job ID
    Spin Memory
    # of Openings
  • Overview



    Spin Memory is at the forefront of innovation with our breakthrough MRAM technologies that are enabling the electronics, digital applications and devices of tomorrow. Join our team of world-class magnetics, circuits and memory architect experts and discover what we can do together.


    Spin Memory is currently seeking a Senior Design Verification Engineer.


    • Plan and implement Full Chip Functional Verification for STT’s MRAM Designs
    • Create and maintain test bench for MRAM Memory Devices using System Verilog
    • Develop behavioral models for analog blocks used within STT’s Memory Devices
    • Identify test coverage measures and provide plan to obtain full test coverage of Memory Devices
    • Work with Design Engineers to provide test benches for Full Chip AMS co-simulations


    • BS/MS in Electrical Engineering with 5+ years experience
    • Strong expertise of Verilog
    • Proficient in System Verilog
    • Understanding of Verification Methodologies like UVM
    • Experience building behavioral models of analog blocks, complex logic blocks and memory arrays
    • Proficiency in scripting languages such as TCL, Perl or Python
    • Past experience with IC Design or Memory Design is highly desirable
    • Expertise in using tools such as Synopsys VCS or Cadence Incisive
    • Experience with simulation tools such as AMS, hspice, hsim, ultrasim, AFS, APS, XA

    Spin Memory is committed to providing equal opportunity for all employees and applicants without regard to race, color, religion, sex, sexual preference/orientation, gender identity or expression, age, marital status, national origin, physical or mental disability, veteran status, or any other protected classification under applicable law.


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