Allied Minds

  • Spin Transfer Technologies - Senior Design Verification Engineer

    Job Locations US-CA-Fremont
    Posted Date 3 weeks ago(6/26/2018 2:03 PM)
    Job ID
    2018-1228
    Name
    Spin Transfer Technologies
    # of Openings
    1
    Category
    Engineering
  • Overview

    STT

     

    Spin Transfer Technologies (STT) is focused on the development of novel magnetoresistive random access memory (MRAM) technologies and devices in collaboration with New York University researchers and industry partners.  STT is currently seeking a Senior Design Verification Engineer.

    Responsibilities

    • Plan and implement Full Chip Functional Verification for STT’s MRAM Designs
    • Create and maintain test bench for MRAM Memory Devices using System Verilog
    • Develop behavioral models for analog blocks used within STT’s Memory Devices
    • Identify test coverage measures and provide plan to obtain full test coverage of Memory Devices
    • Work with Design Engineers to provide test benches for Full Chip AMS co-simulations

    Qualifications

    • BS/MS in Electrical Engineering with 5+ years experience
    • Strong expertise of Verilog
    • Proficient in System Verilog
    • Understanding of Verification Methodologies like UVM
    • Experience building behavioral models of analog blocks, complex logic blocks and memory arrays
    • Proficiency in scripting languages such as TCL, Perl or Python
    • Past experience with IC Design or Memory Design is highly desirable
    • Expertise in using tools such as Synopsys VCS or Cadence Incisive
    • Experience with simulation tools such as AMS, hspice, hsim, ultrasim, AFS, APS, XA

    Spin Transfer Technologies is committed to providing equal opportunity for all employees and applicants without regard to race, color, religion, sex, sexual preference/orientation, gender identity or expression, age, marital status, national origin, physical or mental disability, veteran status, or any other protected classification under applicable law.

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